Design for test (DFT) guidelines related to AOI and AXI
Design guidelines for automated optical inspection (AOI)
The following rules and guidelines ensure that the product (PCBA) can be optimal tested with automated optical inspection. Many AOI/AXI vendors have includes extra features and functions to provide testability even the design for inspection (DFI) guidelines have not been followed to 100%, based on space or functional restrictions, design specifications or limitations of the production equipment.
- Ensure visual access to the component regarding the field of view of the camera and path of the illumination:
THT (Through-Hole-Technology) or other high components could cover small SMT (Surface-Mount Technology) components or parts of ICs. Although angled view cameras can inspect covered components, the inspection and programming time might be longer compared to a clear orthogonal top view.
If possible, install or place shields, heat-sinks or adapters after the optical inspection.
- Use consistent component sizes and land patterns:
By using the IPC standard for land patterns (pads) and component dimensions the programming effort can be reduced. If non-industry standard are used, adjustments in the test parameters and in the model libraries are required. It is also advisable to purchase from the same vendor(s) during the whole production time of one part. Although different vendors offer the same types of components, production date and place may vary.
- Ensure contrast between board (PCB substrate, marking) and component (pin, component body):
Maintain unmarked area around components: Silkscreen markings for the component placements or name could disturb the optical inspection. The algorithms to recognize a part are based on edge detections, therefore a transition between the component and the background are crucial. Such markings would either increase the false calls rate or the programming effort. When small components shall be detected which body color is similar to the board color, a bright silk screen mark underneath and around the part CAD position can help improving the testability (that does not apply for ICs or other components with pins).
Dark PCB substrate beneath device pins: will ensure the inspection of solder bridges between the pins. A bright area would result in a hight false calls rate.
- Avoid alternative layout techniques regarding pad geometries:
In order to inspect the meniscus of a solder joint, two discrete components should not share the same solder pad. Although there are workarounds by creating additional solder joint test steps, the programming effort would be increased.
For similar reasons it is also not advisable to split one pad, e.g place one component (capacitor) on 4 pads.
Avoid shortening pads or pins on purpose, as often seen with ICs. It will disturb the short and solder joint detection.
- List Fiducials in the CAD file:
The AOI system will use fiducials to align the test-program over the PCB. If they are not included, the programmer has to insert them manually or use other markings on the board. Avoid using components as alignment marks.
In case of a paneled board it is advisable to place fiducials on each panel (local) and on the outer edge of the whole board (global).
- Do not populate components on the edge of the PCB:
An AOI system which stands in-line needs to clamp the PCB on the edge – at least 3mm are required for most conveyer systems and machines.
- Maintain a standardized label placement:
Bar-codes or revision markings should be standardized regarding the position, orientation, syntax and format. This can be partly accomplished by using an automatic machine instead of a manual placement.
- Ensure a standardized THT placement:
Often THT components are inserted manually or at least the pins were trimmed by hand. If no automation is possible establish work instructions with dimensions and limits of the clinching and cutting process. Variation through the production process could lead to problem during the THT solder joint inspection on the bottom side of the board.
Design guidelines for automated X-ray inspection (AXI)
The following rules and guidelines ensure that the product (PCB) can be optimal tested with automated optical x-ray inspection system. AXI machines can be divided in two main groups, 2D as orthogonal inspection method with mostly one image per field of view, and the 3D inspection with mostly more than one image per area and at different angles.
- Avoid overlapping solder joints on double-sided PCBs (2D only):
If components of interest are placed at the same position in the top and bottom side, the body or the leads of one part can cover the inspection area of the other part during the 2D x-ray inspection.
- Keep the PCB thickness constant or use a height measurement (3D only):
The exact height of the components during a 3D inspection is of high importance. The best way to ensure the proper calculation is to use a laser measurement system and detect the height of each part.
- Use consistent component sizes and land patterns:
By using the IPC (2220) standard for pad design the test performance can be enhanced. The solder paste stencil should be monitored to ensure a consistent thickness.
If non-industry standard are used, adjustments in the test parameters and in the model libraries are required. It is also advisable to purchase parts from the same vendor(s) during the whole production time of one part. Although different vendors offer the same types of components, production date and place may vary.
- Avoid board warping:
Though warping can be detected by laser and eliminated by the software, it is advisable to avoid it in the first place.
- Avoid filling “via” holes:
Via holes are often filled with solder to access them with the ICT (in-circuit test), but soldered holes can be mistaken for solder shorts by the AXI system.
- Maintain the same pad dimension through the whole project:
Often the pad where pin#1 is placed has another shape or dimension, which will cause modification in the test libraries and therefore a longer programming time.
Contact us for more details or to help you review one of your printed circuit board assemblies for its testability and expected test coverage.