Is IPC-610 sufficient for through-hole inspection?

“IPC-A-610, Acceptability of Electronic Assemblies is the most widely used standard published by the IPC.” (

The “holy book” of PCB manufacturing still lacks the appendix for Automated Optical Inspection (AOI) and Automated X-Ray Inspection (AXI) machines. Though it does regulate limits and rules for the manufacturing, it does not give actual guidelines for the programming of inspection systems. AOI/AXI programmers across the world have worked around this issue by working closely with production and quality engineers to ensure the IPC-610 rules find their way into the automated inspection process. This process is of course not perfect and depends on the experience of the persons involved.

But not only the human-factor is critical, also the actual concept of translating the IPC manufacturing rules into an AOI/AXI program is flawed.

A good example is the evaluation of THT (or PTH) solder joints with an automated 3D X-Ray inspection machine. IPC-610 states that to satisfy quality class 3 a barrel fill of 75% is required. Class 2 requires only 50% barrel fill, as long as conditions are fulfilled. This rule only defines a barrel-fill percentage, which translates into a Z-dimension (height) when inspected with an AXI algorithm. Usually a 3D AXI system would find the slice containing solder that is farthest away from the solder side and provide a height measurement relative to the PCB thickness. However, what happens if there are voids (gas enclosure) within the barrel fill? The height could be well over 75% while the quality if the joint is bad, because there is a large void at 20 % of the barrel height, for example.

Especially in the defense and aerospace industry such week joints could pose serious problems. Manufacturers of printed circuit board assemblies (PCBA) with critical THT joints need to be able to rely on more than the simple 75% IPC barrel-fill rule. Often, manual x-ray system will be used to ensure solder quality in these cases, but why not implement such extra requirements into existing AXI systems?

One such implementation could combine pass / fail criteria instead of relaying just on IPC-610. A true 3D AXI system (such as GOEPEL’s OptiCon X-Line) will reconstruct a certain amount of vertical layer of the PCB. Therefore we know what the solder joint looks like at any given z-level (the focus in this discussion is on the PCB thickness, i.e. the distance from assembly layer [component side] to solder layer [solder side]). If the algorithm calculates the solder area of each slice, it can then calculate the solder volume of the THT joint of interest:

We can then combine the IPC610 height/percentage value with the true volume in a more stringent rule. AXI systems with a flexible programming interface allow more rules to be added or logically combined, such as rules for void dimension, void distribution, void number, solder-volume to solder-height ratio, and so on.

Some may argue that one could measure the solder area per slice, starting at the solder side and stepping through the barrel, and stop when the solder area is below the specified criteria. If at that slice the height (percentage) requirement is not fulfilled one may be tempted to call this solder joint a defect. That is true if one is simply following the IPC specification. However, a small void within that “lower” barrel fill may not affect the solder quality at all, but the IPC rule would result in a failure indication and the board goes to repair or even into the trash bin. Perhaps justified, but maybe overly stringent.

In conclusion, an AXI or AOI system that is able to provide not only one criteria based on the IPC specification but a number of calculated values, allows inspection programs to be better adapted to the product’s quality requirements, while lowering false call rates and avoiding escapes.

Many say that “a tool is only as good as the person who uses it” but I’d add “you can only go as far as your tools allow you to”.

Test Strategy for IoT Devices receives Embedded World 2016 Award

At Embedded World 2016 in Nuremberg, JEDOS (GOEPEL’s test and diagnostics tool for electronic assemblies) received the embedded Award 2016 in the tools category.

With the Embedded Award, a high-ranking jury with representatives from science research, industry, and media recognizes innovative products and solutions that advance the industry of embedded systems and the IoT (Internet of Things) in outstanding ways. 
The award ceremony took place during a press conference by Prof. Matthias Sturm, Chairman of the Advisory Board of the embedded world, and Dr. Roland Fleck, Managing Director of Nürnberg Messe on the first day of Embedded World.

“We are proud of the high recognition our JEDOS test and diagnostic tool enjoys. Winning this award shows us that with our integrated technology platform we’re on the right track”, says Thomas Wenzel, Managing Director of the JTAG/Boundary Scan division of GOEPEL electronic, after accepting the award. “By integrating embedded diagnostics test and JTAG/boundary scan, we are addressing the latest test challenges posed by complex electronic designs, such as Internet of Things components.”

First introduced in 2015, JEDOS is a platform for high-quality embedded tests of complex electronic design. JEDOS offers a variety of functions for test, validation, calibration, and device programming. Using the native processor, diagnostic functional tests can be performed in real time. A key advantage of JEDOS is the possibility to fully test IoT components without the use of firmware. By integrating of boundary scan and functional embedded test and diagnostics, dependable test and fault coverage can be achieved. As a result, firmware and software engineers can benefit from pre-verified prototype hardware, making their development and debug work more efficient.

To learn more about JEDOS, please view this webinar or contact GOEPEL.

Test Optimization in Production through the Use of Boundary Scan

View our latest webinar recording on "Test Optimization in Production - Reduction of Test Time through the Use of Boundary Scan" to learn how you can reduce test time and complex interface hardware through the use of JTAG/Boundary Scan. While Boundary Scan as a test methodology has been around for more than 25 years, its advantages for production test often are still underestimated.And, over the years this technology has seen a lot of innovation.

Designers and test planners alike are confronted with the same problem: to ensure sufficient test access despite increasing miniaturization and simultaneous increase in functionality and complexity of modern electronics. “Every circuit node needs a test point!” Many of you have heard this statement. But this is no longer possible on modern electronics. Join us in this webinar to learn about powerful and cost saving methods to utilize boundary-scan and related technologies in manufacturing test.

Topics that will be addressed during the webinar:

  • "JTAG / Boundary Scan" nowadays is much more than just connectivity test.
  • Utilize the UUT's FPGA or microprocessor as an embedded test system.
  • Testing that previously required high numbers of test probes can still be done when physical external access is no longer possible.


Target audience:  Test engineers, test managers, production engineers, production managers, CEOs, contract designers and contract manufacturers, design engineers and design managers.


Level:  Beginners and advanced users.


This webinar was originally presented on November 3, 2015.

Feel free to view the webinar recording by following this link...