ITC 2011 was fairly busy and we had interesting conversations with attendees. These conversations did not only cover our JTAG / boundary-scan products, such as the upcoming SYSTEM CASCON version 4.6 or the latest developments in ChipVORX, but also IEEE standardization efforts, such as the recently released IEEE Std 1581, the upcoming IEEE P1687 (IJTAG), and changes currently being made in IEEE Std 1149.1.
In our booth we demonstrated the upcoming version of SYSTEM CASCON, specifically a new addition to the user interface, called Mission Assist. This tool will simplify and further automate the test development process by guiding the user through the various steps. Mission Assist enables future extensions with additional graphical development tools. More about that once they become available.
IEEE Std 1581 was finally approved in March 2011 and has been published in June 2011. Heiko Ehrenberg, chair of the IEEE Std 1581 working group, presented a paper at ITC discussing the details of this standard. Furthermore, Heiko answered questions about IEEE Std 1581 at the working group's table during ITC's poster session. Both the presentation and the poster are available for download on the IEEE 1581 working group website, the ITC paper itself can be found on the ITC 2011 proceedings CD.
IEEE P1687 is working hard on completing the draft standard in order to go through the balloting process in 2012. While the hardware specification is pretty much set, work is currently being completed on the ICL (instrument connectivity language) and PDL (procedural description language) specifications.
The last revision of IEEE Std 1149.1 was published in 2001. ICs (integrated circuits) have since become much more complex and designers need to address a wide variety of issues. The IEEE 1149.1 working group is working on updating the standard to provide features and capabilities that make it easier for chip designers to cope with their IC's complexity and still make their JTAG / boundary-scan implementation compliant. The upcoming revision of IEEE Std 1149.1 also addresses issues such as safety (avoiding the "lobotomy" problem, as Dr. Ken Parker calls it), power conservation, and execution of chip-level tests after the IC is part of a printed circuit board assembly. The new revision will introduce a new optional Test Mode Persistence controller, new instructions (IC_RESET, CLAMP_HOLD, CLAMP_RELEASE, INIT_SETUP, _INIT_RUN, ECIDCODE) and associated test data registers, new BSDL attributes, and a new procedural description language (PDL) to support many of the new hardware features. The working group is also discussing issues such as documenting pins and cells that do not support SAMPLE, or the segmentation of test data registers (including potentially the boundary scan register) into different power domains and the control and documentation of such segments.
ITC attendees enjoyed many more interesting topics and discussions. This conference is focused on design for test (DFT), and while a major part of the program is discussing chip level issues and solutions, board and system level applications can only benefit of DFT features implemented in ICs, which is why GOEPEL Electronics has been part of ITC since 1997.