In recent years the trend to more densely packed printed circuit board assemblies (PCBAs) with fewer test points or other opportunities for physical access to signals critical for sufficient test coverage has really taken off. The wide use of ball grid array packaging and signal traces that never surface at the PCBA's top or bottom side are two examples of design features that impact the availability of test access points. This will continue to be problematic and likely get worse. But - embedded system access (ESA) is coming to the rescue. JTAG / boundary scan is one technology that can help regain some of the test access that physical probe based test methodologies are loosing. In addition, the test access port (TAP) interface defined in IEEE Std 1149.1 can be utilized not only for boundary-scan testing but also to access other device internal test and debug capabilities, further enhancing the testability and fault coverage achievable with embedded system access. The diagram on the left illustrates this trend (click on the thumbnail to enlarge the diagram).
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