Testing connections to Memory devices

JTAG / boundary-scan features are implemented in many digital circuits, with one glaring exception: a majority of memory devices do not support IEEE Std 1149.1. The connectivity between a boundary-scan compliant components and such memory devices can then only be tested by means of cluster testing: writing to the memory and reading back pattern written to the memory (while some memory devices may have test modes, often times those test modes are permanently disabled in the board design - not a good thing; board test engineers generally prefer device test modes to be accessible at board and system level).

This cluster testing requires full access to the memory control pins, though. Many SDRAM or similar synchronous memory architectures are implemented on board level with clock circuitry that cannot be synchronized with / controlled by boundary scan. This means that these memory structures cannot be tested via boundary scan in cluster tests.

ITC 2011 poster about IEEE Std 1581A new standard focused on connectivity test on non-boundary scan devices, IEEE Std 1581, has been published in June 2011. This "standard test methodology for memory interconnect testing" defined in IEEE Std 1581 describes test circuitry (to be implemented in a memory device) that bypasses the memory block itself and instead provides a logic connection between input and output pins (using simple logic gates). By stimulating the memory input pins and observing its output pins with boundary-scan devices connected to the memory, board level connectivity can be verified; simplifying and accelerating this kind of test dramatically. The same technology can be applied to and implemented in other (non-memory) slave-type components.

To learn more about IEEE Std. 1581 visit the working group website or contact the working group chair.