JTAG/boundary scan - the “original” ESA technology

We have introduced Embedded System Access (ESA) as a strategy for board and system test in recent blog posts. This is the first of a series of blog posts that will discuss the various ESA technologies in a bit more detail.

The first ESA technology we want to discuss here is the "good old" JTAG / boundary scan.

In 1990, JTAG/boundary-scan was adopted as the IEEE 1149.1 standard. This technology utilizes so called boundary-scan cells, combined into a boundary-scan register, as primary access points for a target system’s circuit nodes. The boundary-scan register is accessed and controlled through the Test Access Port (TAP). All vectors are serially scanned through a test bus, comprised of four mandatory signals and a fifth, optional, reset signal.

Boundary scan is a structural test methodology and provides excellent fault diagnostics, especially for connectivity tests on otherwise hard to access circuit nodes and device pins (such as those on BGA devices, for example). However, since boundary-scan tests are static in nature, dynamic defects usually cannot be detected. In addition to IEEE Std. 1149.1, various related IEEE 1149.x standards have been created or are in development to expand fault coverage.

IEEE Std 1149.1 is currently undergoing a revision by the responsible IEEE working group and an updated standard version is expected for 2013. This new revision will define new optional features, such as device initialization, test data register segmentation, and device reset control, accompanied with updates to the BSDL language and a new procedure description language (PDL) for pattern sequences.

Learn more about JTAG / boundary scandownload a JTAG / boundary-scan tutorial, or download a design for test guidebook.

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