GOEPEL accelerates graphical Boundary Scan Project Development for Multi Board Designs

In cooperation with ASTER TechnologiesGOEPEL electronic has developed a new version of its ScanVision tool suite to solve the problem of multi-board design visualization at the layout and schematic level, enabling a significantly improved level of productivity in project development as well as fault analysis on the production stage.

The increasing utilization of JTAG / boundary-scan technology for the test of complete systems puts new demands on visualization tools, which we are able to meet with our enhanced ScanVision tools”, says Bettina Richter, GOEPEL electronic’s Marketing Manager. “Continuing the long-term cooperation with our partner ASTER, we facilitate the hierarchical utilization of boundary-scan resources throughout the entire product life cycle.

Christophe Lotz, President of ASTER Technologies says: “ASTER is proud to have strong relationships with our strategic partners and have the opportunity to work together in developing advanced technology to meet the ever increasing demands of the boundary scan market.

About the new ScanVision tool suite:

Basically, ScanVision™ consists of the three elements Layout Visualizer, Schematic Visualizer and Virtual Schematic Visualizer. All components are integral parts of the embedded system access (ESA) software SYSTEM CASCON™. A project data base, used consistently by the various tools in the SYSTEM CASCON platform, is generated by importing design data and is then available for comprehensive cross referencing. Tools such as the CASCON Board Merger™ and the CASCON Component Explorer™ are used to merge board design netlists and to associate device models with components that are part of the designs.

Using this information provides opportunities for interactive cross-probing between schematic and layout at pin, component, and net level, and for tracing signal paths even across multiple boards with dynamic switching of the layout or schematic display, assisting operations such as test coverage analysis, hardware debugging, and graphical fault display at board and system level.