IEEE 1149-1

Test Optimization in Production through the Use of Boundary Scan

View our latest webinar recording on "Test Optimization in Production - Reduction of Test Time through the Use of Boundary Scan" to learn how you can reduce test time and complex interface hardware through the use of JTAG/Boundary Scan. While Boundary Scan as a test methodology has been around for more than 25 years, its advantages for production test often are still underestimated.And, over the years this technology has seen a lot of innovation.

Designers and test planners alike are confronted with the same problem: to ensure sufficient test access despite increasing miniaturization and simultaneous increase in functionality and complexity of modern electronics. “Every circuit node needs a test point!” Many of you have heard this statement. But this is no longer possible on modern electronics. Join us in this webinar to learn about powerful and cost saving methods to utilize boundary-scan and related technologies in manufacturing test.

Topics that will be addressed during the webinar:

  • "JTAG / Boundary Scan" nowadays is much more than just connectivity test.
  • Utilize the UUT's FPGA or microprocessor as an embedded test system.
  • Testing that previously required high numbers of test probes can still be done when physical external access is no longer possible.

 

Target audience:  Test engineers, test managers, production engineers, production managers, CEOs, contract designers and contract manufacturers, design engineers and design managers.

 

Level:  Beginners and advanced users.

 

This webinar was originally presented on November 3, 2015.

Feel free to view the webinar recording by following this link...

New mixed-signal JTAG I/O module

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CION LX module FXT96 At International Test Conference (ITC) 2014 in Seattle, GOEPEL Electronics introduced the CION-LX Module/FXT96, a new mixed-signal JTAG I/O module enabling boundary-scan based tests to non scannable circuit components such as connectors, clusters, or analog interfaces.

CION-LX Module/FXT96 supports test standards such as IEEE 1149.1, IEEE 1149.6, and IEEE 1149.8.1. The module provides 96 single-ended, 12 High Current, and 24 differential test channels. Each channel is bi-directional and their parameters can be configured. Unique in the industry, dynamic test resources such as frequency counter, event detector, arbitrary waveform generator and digitizer are available. This new module is based on CION-LX™, a JTAG controllable Mixed Signal Tester-on-Chip (ToC), developed by GOEPEL electronics.

“We set entirely new standards with the new CION-LX Module/FXT96 in regards to flexibility and functionality of JTAG controlled I/O modules”, says Heiko Ehrenberg of GOEPEL Electronics USA. “We can offer our customers a simple, safe, and affordable solution to enhance their boundary-scan application significantly. With the test resources available per channel, both static and dynamic at-speed-tests are possible – which means significant improvement of structural test coverage and even more flexible test strategies for our customers.”

CION-LX Module/FXT96 can be connected to any Test Access Port (TAP) and can be cascaded to increase the number of channels. It can be operated in combination with other CION modules™ or ChipVORX modules™. Using the boundary-scan software platform SYSTEM CASCON™ a comprehensive automation of the entire project development is possible with minimal effort. Detected errors can be immediately displayed graphically in the PCBA layout with the Scan Vision™ tools. CION-LX Module/FXT96 can be used both for prototype test in the laboratory as well as in production.

JTAG / Boundary Scan Compliance Awareness

The JTAG interface is becoming more complex as vendor tools seek to take advantage of a wide range of applications possible.

Traditionally, the JTAG interface has been used for board-level testing based on the Std. IEEE 1149.1 (also known as Boundary Scan).  The standard was first adopted in the early 90's and since then, the JTAG interface has morphed into an interface that is not only used for test purposes.  Furthermore, not all applications utilized over JTAG have been standardized as has been done Std IEEE 1149.1.  The broad range of applications made possible over the JTAG interface have introduced new challenges for compatibility; many applications using the JTAG interface may not be fully compliant with IEEE Std 1149.1 unless special measures are taken into consideration.

IEEE Std 1149.1 includes rules about compliance:  if a device requires a compliance condition, the standard mandates this condition must be specified in the BSDL file associated with the component.  A static level (high or low, as defined in the BSDL file) asserted to "compliance pin(s)" (or "compliance enable pin(s)"), must enable the device to become IEEE 1149.1 compliant.

Not all JTAG devices have compliance pins; only those that require an "extra" condition for the device to be JTAG compliant.

Unfortunately, this "extra" condition is not always implemented as an IEEE 1149.1 compliance pin as mandated by the standard.  A device may require a special pattern or sequence of conditions (usually during power-on reset) before it becomes JTAG compliant.  However, these special conditions may not be clearly defined in the BSDL file because a simple static level applied to a pin is not enough for the device to be in compliance.  For example, the "extra" condition may be a sequence of H's and L's that must be exercised on a MODE input pin after the device is powered on.  Or, it could be a series of values clocked into the the JTAG TAP signals (TCK, TMS, TDI, TDO) before the 1149.1 TAP interface becomes active.

These special conditions that don't behave as compliance pins pose challenges for design and test engineers - it is not always sufficient to consult the BSDL file to determine JTAG compliance conditions; sometimes one must delve deeper into device specific requirements outlined in the datasheet or reference manual.  For devices with multiple modes of operation (e.g. Debug / emulation mode + JTAG), the JTAG interface requirements are usually clearly documented in the reference manual.

If you are seeing compliance issues in devices you are using in your designs, contact a GOEPEL application engineer to discuss possible solutions.