IEEE 1149-7

JTAG / Boundary Scan Compliance Awareness

The JTAG interface is becoming more complex as vendor tools seek to take advantage of a wide range of applications possible.

Traditionally, the JTAG interface has been used for board-level testing based on the Std. IEEE 1149.1 (also known as Boundary Scan).  The standard was first adopted in the early 90's and since then, the JTAG interface has morphed into an interface that is not only used for test purposes.  Furthermore, not all applications utilized over JTAG have been standardized as has been done Std IEEE 1149.1.  The broad range of applications made possible over the JTAG interface have introduced new challenges for compatibility; many applications using the JTAG interface may not be fully compliant with IEEE Std 1149.1 unless special measures are taken into consideration.

IEEE Std 1149.1 includes rules about compliance:  if a device requires a compliance condition, the standard mandates this condition must be specified in the BSDL file associated with the component.  A static level (high or low, as defined in the BSDL file) asserted to "compliance pin(s)" (or "compliance enable pin(s)"), must enable the device to become IEEE 1149.1 compliant.

Not all JTAG devices have compliance pins; only those that require an "extra" condition for the device to be JTAG compliant.

Unfortunately, this "extra" condition is not always implemented as an IEEE 1149.1 compliance pin as mandated by the standard.  A device may require a special pattern or sequence of conditions (usually during power-on reset) before it becomes JTAG compliant.  However, these special conditions may not be clearly defined in the BSDL file because a simple static level applied to a pin is not enough for the device to be in compliance.  For example, the "extra" condition may be a sequence of H's and L's that must be exercised on a MODE input pin after the device is powered on.  Or, it could be a series of values clocked into the the JTAG TAP signals (TCK, TMS, TDI, TDO) before the 1149.1 TAP interface becomes active.

These special conditions that don't behave as compliance pins pose challenges for design and test engineers - it is not always sufficient to consult the BSDL file to determine JTAG compliance conditions; sometimes one must delve deeper into device specific requirements outlined in the datasheet or reference manual.  For devices with multiple modes of operation (e.g. Debug / emulation mode + JTAG), the JTAG interface requirements are usually clearly documented in the reference manual.

If you are seeing compliance issues in devices you are using in your designs, contact a GOEPEL application engineer to discuss possible solutions.

What is “JTAG”?

When most test or design engineers hear "JTAG", many things may come to mind.  The acronym itself stands for Joint Test Action group -- a user group who initialized the IEEE 1149.1 standard, also known as boundary scan.  However, since its inception as the first sanctioned IEEE test standard, JTAG has evolved to embody a variety of applications not included in the originally drafted IEEE 1149.1 standard.  Nowadays, the JTAG term is not very straightforward and often ambiguous.  Today, the JTAG interface is utilized for a range of applications.

Below are some common JTAG applications:

1.) Conventional IEEE 1149.1 / boundary scan (board-level test)

2.) In-System Programming (ISP) or Configuration of PLDs/FPGAs

3.) Flash programming

4.) On-chip debug / On-chip emulation (for processors)

5.) Built-in self test (BIST)

The most common definition for JTAG is probably (1.) where the interface is utilized for testing connectivity between devices on a PCB.  There are many other value added resources besides connectivity testing.  For example, another common JTAG application is In-system programming (ISP).  Via ISP, it is possible to program / configure FPGAs and CPLDs.   This has an advantage of programming configurable devices after they are mounted on the board, offering the ability to make design changes later in the product life cycle.

The JTAG port is not limited to shifting test vectors through the boundary scan registers.   Many processors allow access to embedded resources via the JTAG interface bypassing the boundary scan registers, and instead, using a debug port interface.  This is often referred to as On-chip debug, On-chip emulation (OnCE), or Processor Emulation.  One can think of the JTAG interface as providing a "backdoor" for emulating the processor.

Other JTAG applications comprise of self-test methods for chips or System-on-Chips (SoCs).  In contrast to board-level test which focuses on capturing manufacturing defects, self-test aims to test the internal properties of the chip or SoC.  Built-in self test (BIST) methods can be incorporated by device manufacturers as a way to test internal chip resources at-speed.  Other standards, such as IEEE 1500, focus on testing SoC resources by including an additional wrapper as part of the JTAG interface.

The applications discussed in this article are by no means the entire list of possible JTAG applications. We encourage you to explore other possibilities with JTAG.  You may surprise yourself with what's possible. Click here for information on JTAG technology related standards

GOEPEL announces Embedded System Access (ESA) strategy

At IPC APEX 2012, we demonstrated version 4.6 of our Boundary Scan software platform SYSTEM CASCON™. With this version we are introducing the concept of Embedded System Access (ESA) technologies. Embedded System Access stands in contrast to intrusive board access (IBA) techniques, such as bed-of-nail or flying-probe based in-circuit test, and native connector access, as commonly applied for functional test. Yet, ESA and these other access techniques do not necessarily have to be used exclusively, but rather can be combined in integrated test solutions.

Modern printed circuit board assemblies (PCBAs) provide increasing functionality, often coupled with a high degree of complexity and integration, with limited physical access through physical probing (intrusive board access). Sufficient access is the central problem for all test methodologies. Embedded System Access (ESA) technologies enable the use of standardized instrumentation platforms throughout the entire product life cycle, allowing the reuse of existing applications and increasing the fault coverage of production tests. ESA is primarily based on access through the JTAG port defined in IEEE 1149.1 (or IEEE 1149.7) and on test resources defined in those and other related standards (such as IEEE 1149.4, IEEE 1149.6, IEEE 1500, and the upcoming IEEE P1687, for example). The following graphic shows a classification of major access techniques and test methodologies:

Mult-idimensional JTAG / boundary-scan instrumentation

GOEPEL Electronics supports all ESA techniques through its VarioCORE, VarioTAP, and ChipVORX technologies, fully integrated in the software platform SYSTEM CASCON. Furthermore, such ESA applications can be combined with other test techniques through various integration packages and technologies such as HyScan and Virtual ScanPin.

To learn more about Embedded System Access, please contact us to request a White Paper on the topic or ontact one of our application engineers for a discussion and/or demo.