The JTAG interface is becoming more complex as vendor tools seek to take advantage of a wide range of applications possible.
Traditionally, the JTAG interface has been used for board-level testing based on the Std. IEEE 1149.1 (also known as Boundary Scan). The standard was first adopted in the early 90's and since then, the JTAG interface has morphed into an interface that is not only used for test purposes. Furthermore, not all applications utilized over JTAG have been standardized as has been done Std IEEE 1149.1. The broad range of applications made possible over the JTAG interface have introduced new challenges for compatibility; many applications using the JTAG interface may not be fully compliant with IEEE Std 1149.1 unless special measures are taken into consideration.
IEEE Std 1149.1 includes rules about compliance: if a device requires a compliance condition, the standard mandates this condition must be specified in the BSDL file associated with the component. A static level (high or low, as defined in the BSDL file) asserted to "compliance pin(s)" (or "compliance enable pin(s)"), must enable the device to become IEEE 1149.1 compliant.
Not all JTAG devices have compliance pins; only those that require an "extra" condition for the device to be JTAG compliant.
Unfortunately, this "extra" condition is not always implemented as an IEEE 1149.1 compliance pin as mandated by the standard. A device may require a special pattern or sequence of conditions (usually during power-on reset) before it becomes JTAG compliant. However, these special conditions may not be clearly defined in the BSDL file because a simple static level applied to a pin is not enough for the device to be in compliance. For example, the "extra" condition may be a sequence of H's and L's that must be exercised on a MODE input pin after the device is powered on. Or, it could be a series of values clocked into the the JTAG TAP signals (TCK, TMS, TDI, TDO) before the 1149.1 TAP interface becomes active.
These special conditions that don't behave as compliance pins pose challenges for design and test engineers - it is not always sufficient to consult the BSDL file to determine JTAG compliance conditions; sometimes one must delve deeper into device specific requirements outlined in the datasheet or reference manual. For devices with multiple modes of operation (e.g. Debug / emulation mode + JTAG), the JTAG interface requirements are usually clearly documented in the reference manual.
If you are seeing compliance issues in devices you are using in your designs, contact a GOEPEL application engineer to discuss possible solutions.