IEEE 1581

Testing connections to Memory devices

JTAG / boundary-scan features are implemented in many digital circuits, with one glaring exception: a majority of memory devices do not support IEEE Std 1149.1. The connectivity between a boundary-scan compliant components and such memory devices can then only be tested by means of cluster testing: writing to the memory and reading back pattern written to the memory (while some memory devices may have test modes, often times those test modes are permanently disabled in the board design - not a good thing; board test engineers generally prefer device test modes to be accessible at board and system level).

This cluster testing requires full access to the memory control pins, though. Many SDRAM or similar synchronous memory architectures are implemented on board level with clock circuitry that cannot be synchronized with / controlled by boundary scan. This means that these memory structures cannot be tested via boundary scan in cluster tests.

ITC 2011 poster about IEEE Std 1581A new standard focused on connectivity test on non-boundary scan devices, IEEE Std 1581, has been published in June 2011. This "standard test methodology for memory interconnect testing" defined in IEEE Std 1581 describes test circuitry (to be implemented in a memory device) that bypasses the memory block itself and instead provides a logic connection between input and output pins (using simple logic gates). By stimulating the memory input pins and observing its output pins with boundary-scan devices connected to the memory, board level connectivity can be verified; simplifying and accelerating this kind of test dramatically. The same technology can be applied to and implemented in other (non-memory) slave-type components.

To learn more about IEEE Std. 1581 visit the working group website or contact the working group chair.

What is “JTAG”?

When most test or design engineers hear "JTAG", many things may come to mind.  The acronym itself stands for Joint Test Action group -- a user group who initialized the IEEE 1149.1 standard, also known as boundary scan.  However, since its inception as the first sanctioned IEEE test standard, JTAG has evolved to embody a variety of applications not included in the originally drafted IEEE 1149.1 standard.  Nowadays, the JTAG term is not very straightforward and often ambiguous.  Today, the JTAG interface is utilized for a range of applications.

Below are some common JTAG applications:

1.) Conventional IEEE 1149.1 / boundary scan (board-level test)

2.) In-System Programming (ISP) or Configuration of PLDs/FPGAs

3.) Flash programming

4.) On-chip debug / On-chip emulation (for processors)

5.) Built-in self test (BIST)

The most common definition for JTAG is probably (1.) where the interface is utilized for testing connectivity between devices on a PCB.  There are many other value added resources besides connectivity testing.  For example, another common JTAG application is In-system programming (ISP).  Via ISP, it is possible to program / configure FPGAs and CPLDs.   This has an advantage of programming configurable devices after they are mounted on the board, offering the ability to make design changes later in the product life cycle.

The JTAG port is not limited to shifting test vectors through the boundary scan registers.   Many processors allow access to embedded resources via the JTAG interface bypassing the boundary scan registers, and instead, using a debug port interface.  This is often referred to as On-chip debug, On-chip emulation (OnCE), or Processor Emulation.  One can think of the JTAG interface as providing a "backdoor" for emulating the processor.

Other JTAG applications comprise of self-test methods for chips or System-on-Chips (SoCs).  In contrast to board-level test which focuses on capturing manufacturing defects, self-test aims to test the internal properties of the chip or SoC.  Built-in self test (BIST) methods can be incorporated by device manufacturers as a way to test internal chip resources at-speed.  Other standards, such as IEEE 1500, focus on testing SoC resources by including an additional wrapper as part of the JTAG interface.

The applications discussed in this article are by no means the entire list of possible JTAG applications. We encourage you to explore other possibilities with JTAG.  You may surprise yourself with what's possible. Click here for information on JTAG technology related standards