The innovative TAP Checker tool suite enables automated generation of simulation vectors and test patterns for chip-level validation and verification of IEEE 1149.1 and IEEE 1149.6 compliant implementation.

 

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Features and Benefits:

  • Automated generation of test bench for validation and 
  • verification of JTAG / boundary scan designs;
  • Tool flow includes BSDL verification (syntax and semantics);
  • Supporting IEEE 1149.1 and IEEE 1149.6;
  • Support for multi-chip modules and 3-D silicon devices;
  • Output formats: Verilog (IEEE 1364), VHDL (IEEE 1076), and STIL (IEEE 1450);
  • For Sun Solaris, Linux, and Windows; GUI and command line interface;

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